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M65667FP
Picture-in-Picture Signal Processing
REJ03F0185-0201 Rev.2.01 Mar 31, 2008
Description
The M65667FP is a NTSC PIP (Picture in Picture) signal processing LSI, whose sub and main-picture inputs are composite and Y/C separated signals, respectively. The built-in field memory (96 Kbit RAM), V-chip data slicer and analog circuitries lead the PIP system low cost and small size.
Features
* * * * * Built-in 96 Kbit field memory (sub-picture data storage) Internal V-chip data slicer (for sub-picture) Vertical filter for sub-picture (Y signal) Single sub-picture (selectable picture size: 1/9, 1/16) Sub-picture processing specification (1/9 size / 1/16 size) Quantization bits Y, B-Y, R-Y: 6 bits Horizontal sampling 171 pixels (Y), 28.5 pixels (B-Y, R-Y) Vertical lines 69/52 lines * Frame (sub-picture) on/off * Built-in analog circuits Two 8-bit A/D converters (main and sub-picture signals) Two 8-bit D/A converters (Y and C sub-picture signals) Sync-tip-clamp, VCXO, Analog switch, etc. * I2C BUS control (parallel/serial control) PIP on/off, Sub-picture size (1/9 or 1/16), Frame on/off (programmable luma level), PIP position (4 corners fixed position), Picture freeze, Y delay adjustment, Chroma level, Tint, Black level, Contrast, etc.
Application
NTSC color TV
Recommended Operating Condition
Supply voltage range ................................. 3.1 to 3.5 V Operating frequency ................................. 14.32 MHz Operating temperature .............................. -20 to 75C Input voltage (CMOS interface) "H" ............... Vdd 0.7 to Vdd V "L" ............... 0 to Vdd 0.3 V Output current (output buffer) ..................... 4 mA (Max) Output load capacitance ........................... 20 pF (Max) Note2 Circuit current ....................................... 160 mA Notes: 1. Connect a 0.1 F or larger capacitor between Vdd and Vss pins. 2. Include pin capacitance (7 pF)
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 1 of 12
M65667FP
Block Diagram
SCK CSYNC (s) /TEST1 BGP (s) /TEST0
Yin Sync tip clamp Cin Vdd/Vss For test DATA CLK ACK Vin (s) 15 3 3 I2C I/F A/D 8 bit RAM (1H) V-chip data slicer Luma clamp Delay Y 6 Back porch clamp AFC Timing gen (Decode) B-Y Demod Tint R-Y 6 6 Y B-Y R-Y Timing gen (Memory cont) Vert-filter & MUX Bias
Y-PlP Bias C-PlP
C-PlPin
Y Y/C SEP (LPF, BPF)
Sync tip clamp 2 HD (I C)
2
Y-PlPin
Vrt (m) Vrb (m)
Sync sep Phase select HPLL 4 fsc Delay C
SWMG /TEST7
ADJ-Ysub Yout-sub D/A 8 bit D/A 8 bit
Demux
Delay MIX
Delay LPF &MPY
6
Y RAM 96 Kbits
Encode
6 B-Y 6 R-Y
VD /CSYNC /TEST6 HD /TEST5 FILTER
Cout-sub
fsc Level detect
ADJ-Csub Vin (m) Bias A/D 8 bit
Burst data sampling
Phase detect Lock/Free-run via I2C VCXO driver
BIAS 4 fsc VCXO in VCXO VCXO out
Vrt (m) Vrb (m)
2
RESET
MCK
BGP (m) /TEST2
fsc /TEST3
SWM /TEST4
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 2 of 12
M65667FP
Pin Arrangement
M65667FP
34 LOCK/TEST7 47 AVdd4 (da) 46 AVdd4 (da) 45 AVdd4 (da) 43 AVss4 (da) 42 AVss4 (da)
38 ADJ-Csub
40 ADJ-Ysub
37 Cout-sub
39 Yout-sub
44 C-PlPin
41 Y-PlPin
35 DVdd3
36 DVss3
48 C-PlP
NC 49 TEST8 50 Y-PlP 51 TEST9 52 Yin 53 TESTEN 54 Cin 55 AVss (ana) 56 AVss3 (vcxo) 57 VCXO out 58 VCXO in 59 FILTER 60 BIAS 61 AVdd3 (vcxo) 62 AVdd2 (m) 63 AVdd2 (m) 64
Vrb (s) 10 AVss1 (s) 12 RESET 13 DVss1 14 DVdd1 15 AVss2 (m) 4 AVss2 (m) 5 AVdd1 (s) 6 AVdd1 (s) 7 AVss1 (s) 11 Vin (m) 1 Vrt (m) 2 Vrb (m) 3 Vin (s) 8 Vrt (s) NC 16
9
33 NC
32 NC 31 VD/CSYNC/TEST6 30 HD/TEST5 29 SWM/TEST4 28 MCK 27 fsc/TEST3 26 BGP (m)/TEST2 25 DVdd2 (ram) 24 DVss2 (ram) 23 CLK 22 DATA 21 ACK 20 CSYNC (s)/TEST1 19 SCK 18 BGP (s)/TEST0 17 NC
NC: No connection
(Top view) Outline: PRQP0064GA-A (64P6N-A)
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 3 of 12
M65667FP
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name Vin (m) Vrt (m) Vrb (m) AVss2 (m) AVss2 (m) AVdd1 (s) AVdd1 (s) Vin (s) Vrt (s) Vrb (s) AVss1 (s) AVss1 (s) RESET DVss1 DVdd1 NC NC BGP (s) /TEST0 SCK CSYNC (s) /TEST1 ACK DATA CLK DVss2 (ram) DVdd2 (ram) BGP (m) /TEST2 fsc/TEST3 MCK SWM/TEST4 HD/TEST5 VD/CSYNC/TEST6 NC NC SWMG/TEST7 DVdd3 DVss3 Cout-sub ADJ-Csob Yout-sub ADJ-Ysub Y-PIPin AVss4 (da) AVss4 (da) C-PIPin AVdd4 (da) AVdd4 (da) AVdd4 (da) C-PIP I/O I O O GND GND Vdd Vdd I O O GND GND I GND Vdd -- -- (I/) O I I (/O) O I I GND Vdd (I/) O I (/O) I (I/) O I (/O) I (/O) -- -- I (/O) Vdd GND O I O I I GND GND I Vdd Vdd Vdd O Function Chroma signal input (main-picture) A/D Vref+ (main-picture) A/D Vref- (main-picture) Connect to analog GND Connect to analog GND Connect to analog power supply Connect to analog power supply Composite video signal input (sub-picture) A/D Vref+ (sub-picture) A/D Vref- (sub-picture) Connect to analog GND Connect to analog GND Power on reset input signal ("L" reset) Connect to digital GND Connect to digital power supply No connection No connection For test For test (connect to digital GND) For test (connect to digital GND) I2C bus-data/Acknowledge output signal I2C bus-data input signal I2C bus-clock input signal Connect to digital GND Connect to digital power supply For test For test (pull down to digital GND by resistor 15 k) For test (connect to digital GND) For test Horizontal sync input signal (Positive going edge is used) Vertical sync input signal (active "H") No connection No connection Enable input signal to display sub picture ("H" enable) Connect to digital power supply Connect to digital GND D/A output signal (Chroma signal of sub-picture) D/A adjust for chroma signal (sub-picture) D/A output signal (Luma signal of sub-picture) D/A adjust for luma signal (sub-picture) PIP luma signal re-input Connects to analog GND Connects to analog GND PIP chroma signal re-input Connect to analog power supply Connect to analog power supply Connect to analog power supply PIP chroma signal output Non connect Connect to GND Pull down 15 k Remarks
100 k to Vdd, 10 F to GND
Non connect Pull down 15 k Connect to GND Non connect
Pull down 15 k
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 4 of 12
M65667FP
Pin Description (cont.)
Pin No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name NC TEST8 Y-PIP TEST9 Yin TESTEN Cin AVss (ana) AVss3 (vcxo) VCXO out VCXO in FILTER BIAS AVdd3 (vcxo) AVdd2 (m) AVdd2 (m) I/O -- I O I I I I GND GND O I I O Vdd Vdd Vdd Function No connection For test (connect to analog GND) PIP luma signal output For test (connect to analog GND) Luma input signal (main-picture) For test (connect to analog GND) Chroma input signal (main-picture) Connect to analog GND Connects to analog GND VCXO output signal VCXO input signal Filter Bias Connect to analog power supply Connect to analog power supply Connect to analog power supply Remarks Pull up 15 k Connect to GND Connect to GND
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 5 of 12
M65667FP
Absolute Maximum Ratings
(Vss = 0 V)
Limits Item Supply voltage (3.3 V) Input voltage Output voltage Output current Note1 Power dissipation Operating temperature Storage temperature Note: VDD3 VI VO IO Pd Topr Tstg Symbol Min -0.3 -0.3 -0.3 -- -- -20 -50 Max 4.6 VDD3 + 0.3 VDD3 + 0.3 IOL = 20 IOH = -26 1400 75 125 Unit V V V mA mW C C
1. Output current per output terminal. But Pd limits all current.
Thermal Derating (Maximum Rating)
2000
Power Dissipation Pd (mW)
1600
1280
1200
800 400
0 0 25 50 75 100 125
Ambient Temperature Ta (C)
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 6 of 12
M65667FP
DC Characteristics
(Ta = 25C, unless otherwise noted, Vss = 0 V)
Item Input voltage (CMOS interface) Input voltage schmitt trigger (CMOS interface) Output voltage Output current Input current Output leakage current Input pin capacitance Output pin capacitance Bidirectional pin capacitance Operating current 3.3 V supply L H - + Hysteresis L H L H L H L H Symbol VIL VIH VT- VT+ VH VOL VOH IOL IOH IIL IIH IOZL IOZH CI CO CIO IDD Min 0 2.52 0.5 1.4 0.3 -- 3.25 4 -- -1 -1 -1 -1 -- -- -- -- Limits Typ -- -- -- -- -- -- -- -- -- -- -- -- -- 7 7 7 -- Max 0.81 3.6 1.65 2.4 1.2 0.05 -- -- -4 1 1 1 1 15 15 15 140 Unit V V V V V V V mA mA A A A A pF pF pF mA Test Conditions VDD = 2.7 V VDD = 3.6 V VDD = 3.3V
VDD = 3.3 V, |IO| < 1 A VDD = 3.0 V, VOL = 0.4 V VDD = 3.0 V, VOH = 2.6 V VDD = 3.6 V, VI = 0 V VDD = 3.6 V, VI = 3.6 V VDD = 3.6 V, VO = 0 V VDD = 3.6 V, VO = 3.6 V f = 1 MHz, VDD = 0 V
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 7 of 12
M65667FP
PIP TV System Block Diagram
(BASIC) Y C C BLPLL B-LD Y C CV PIP signal processing Y C
Composite video signal
Y/C Separation
Y
M65667FP Y C Video signal processing
Deflection unit Yoke
Y/C separated video signal
+
HD
VD
Driving Method and Operating Specification for Serial Interface Data (1) Serial data transmission completion and start A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the serial transmission and makes the bus free. A high-to-low transition of the DATA line while the CLK is high, that starts the serial transmission and waits for the following CLK and DATA inputs. (2) Serial data transmission The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. One-byte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for acknowledge detection. (In reading state, ACK is "H" under these two conditions; 1. The coincidence of two address data for the address data transmission. 2. The completion of 8-bit setting data transfer. In writing state, ACK is "H" with the address coincidence and ACK is "L" for detecting acknowledge input from the master (micro processor) after sending 8-bit setting data). For address/data transmission, DATA must change while CLK is "L". (The data change while CLK is "H" or the simultaneous change of CLK and DATA, that will be a false operation because of undistinguished condition from the completion/start of serial data transfer.) After the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited. (3) The byte format of data transmission (The sequence of data transmission) 1. The byte format during data setting to M65667FP are shown as follows. In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards, the internal register address (1 byte) and setting data (by 1 byte unit) are transferred successively. Several bytes of setting data can be handled in the one transmission. In this operation, the setting data are written into the address resister whose address is increased one in initially transferred internal register address. (The next address of 7Fh, it returns to 00h.) 2. The byte format during data reading from M65667FP are shown as follows. Before data reading from M65667FP, whose internal address need to be set by the data reading/transmitting. After the data reading/transmitting, the operation of "serial data transmission completion and start" (described in (1)) is necessary. Continuously, the slave address 25h (00100101b) is sent, and then the inverted read out data are available on ACK. Several bytes of writing data can be handled in the one transmission, too. In this operation, the setting data also are written into the address register whose address is increased one in initially transferred internal register address. (The next address of 7Fh, it returns to 00h.)
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 8 of 12
M65667FP The Examples of Serial Byte Transmission Format (1) The writing operation of the setting data (AAh) into M65667FP internal address of 00h
Transmission activation Confirmation of bus free (DATA = 'H') No is applied on CLK for the release of output state S: Operation of serial transmission start A: Acknowledge detection D: Dummy clock feed for the release of acknowledge output state E: Operation of serial transmission completion Yes
S
24h
A
00h
A
AAh
ADE
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65667FP internal address of 04h to 06h
Confirmation of bus free (DATA = 'H') No is applied on CLK for the release of output state Yes
Transmission activation
S
24h
A
04h
A
FFh
A
80h
A
EEh
ADE
(3) The reading operation of the setting data from M65667FP internal address of 00h
Confirmation of bus free (DATA = 'H') No A: Bus free operation by the master (micro processor) is applied on CLK for the release of output state Yes
Transmission activation
S
24h
A
00h
ADES
25h
A
$$h
A
(4) The reading operation of the setting data from M65667FP internal address of 04h to 06h
Confirmation of bus free (DATA = 'H') No is applied on CLK for the release of output state A: Output L operation by the master (micro processor) Yes
Transmission activation
S
24h
A
04h
ADES
25h
A
$$h
A
$$h
A
$$h A
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 9 of 12
M65667FP
Timing Diagram
(1) (2) (3) (4) (5) (6) (7) (8) (9) (1)
CLK
DATA
Bit7 (MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (LSB)
ACK Detec.
Bit7 (MSB)
ACK _Acknowledge
ACK _Readout data
Bit7 (MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (LSB)
Bit7 (MSB)
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 10 of 12
M65667FP
Application Example
Sub-picture displaying on/off Horizontal sync input signal (main-picture) PIP Chroma signal output Vertical sync input signal (main-picture)
33 32 31 30 29 28
Ana. 68 pF Ana. 10 F 103 F 104 F
+
470 Ana. 150 pF 103 F 360 103 F Dig 10 F
104 F
43 42 41 40 39 38 37
103 F
36 35 34
48 49 50 51 52
47
46
45
44
+
15 k Ana. PIP Luma signal output Luma signal input (main-picture) Chroma input signal (main-picture) 104 F
53 54
10 k 15 k Dig + 10 F Dig 5 V 12 k 47 k 10 k Dig 5 V 12 k 47 k 100 100 100 SCL SDA
27 26
104 F
55 56
M65667FP
25 24 23 22 21 20 19 18 17
103 F
51 14 pF 104 F 330 103 F Ana. + 10 F 103 F 2 k 3.3 F 100 k 470 k
57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
560 330
Digital +3.3 V power supply Digital GND Ana. Analog +3.3 V power supply Analog GND Ana.
104 F 103 F 103 F 10 F
+
103 F 103 F 10 F
+
100 k +
103 F Ana. SYNC SEP Circuit (Optional)
103 F 104 F
10 F Dig
Composite video input signal (sub-picture)
+
Note:
Separate Y/C signals by using LC-tank circuit or LPF, BPF for Y/C signals level adjust. And then mix both signals for sub-picture input video signal.
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 11 of 12
I2C BUS DATA input/output signal
I2C BUS Clock input signal
M65667FP
Package Dimensions
JEITA Package Code P-QFP64-14x14-0.80 RENESAS Code PRQP0064GA-A Previous Code 64P6N-A MASS[Typ.] 1.1g
HD *1 D 33
48
49
32
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
HE
E
17
ZE
64
Reference Symbol
Dimension in Millimeters
1 ZD
16 Index mark F
c
L Detail F
D E A2 HD HE A A1 bp c e y ZD ZE L
e
y
*3 b p
Min Nom Max 13.8 14.0 14.2 13.8 14.0 14.2 2.8 16.5 16.8 17.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0 10 0.65 0.8 0.95 0.10 1.0 1.0 0.4 0.6 0.8
REJ03F0185-0201 Rev.2.01 Mar 31, 2008 Page 12 of 12
A1
A
A2
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